Braccio provided verification reuse for an ARM-based system-on-chip (SoC) using Verisity’s Specman Elite and applicable “e” language-verification components, called eVCs. Developers have applied Braccio to two large ASIC projects of several million gates, and it has proved useful for the verification of complex modules that were not easily verified using traditional techniques and testbenches.
The particular HDL language employed on a given project is a function of geographic and personal preference, performance, previous experience, existing tools and capabilities. These contingencies and ever-shifting influences lead to frequent changes in HDL languages and hardware simulators. The functional verification environment should be isolated from these frequent changes by existing independently of the hardware language and simulators.
Braccio uses Specman Elite to abstract the names and hierarchy of the hardware. Computed names in e allow for the binding of a string to a hardware signal or register name. Changes to the hardware naming are accommodated simply by changing this binding; nothing else is necessary. Similarly, units define an “hdl_path” that acts as a string prefix to the above signals, allowing the hardware module to be moved to an arbitrary place in the hardware hierarchy.
Transactor independence is also important. Braccio uses a designed bus-specific transactor interface to abstract the differences between several transactor environment implementations. Tests are reusable from the module to system level. Reusing tests developed at the module level for higher integrations of subsystem and system-level testing allows for a quick determination of the integrity of the device integration. Basic problems with connections and device operation in the context of the system are found quickly.
Braccio uses various modularization techniques to allow module-level verification environments to be merged easily to form a subsystem or full-chip environment. Most aspects of the module-level environment use explicit objects that ensure clean name spaces. Memory maps are determined from the specification before the first module-level environment is created. Replacement of a behavioral model with a design module in the e code is a single constraint for the Verisity eVCs. Instantiation of additional modules is a simple specification to a Mint-written program, netgen, which builds the HDL portion of the testbench.
Additionally, Braccio places an infinite queue between the test and the transactors. Independent test threads can then be seamlessly brought together to utilize the same master with the queue serializing the requests. Thus in the case of mimicking CPU activity in an SoC, separate “programs” and interrupt service routines can run concurrently without a problem. Fancier queuing and scheduling algorithms could be created for more accurate embedded-OS modeling. Tests are executable in simulation and on actual hardware. Tests that can be run both in the lab (on actual hardware) and in the simulation environment provide more opportunities for reuse. Such a capability allows presilicon verification engineers to leverage existing system firmware/software and allows post-silicon system integrators to leverage verification code run before device fabrication.
Braccio also emphasizes maintainability. A verification environment must be maintainable both during a project and from project to project if it is to be reused.
Braccio uses a Mint-based source control management (SCM) system, Mint Source Control (MSC), that enables a hierarchy of source code components to be combined seamlessly into one project environment. Components undergo their own release cycles since they are used independently on many projects. Future projects can choose only those components that are applicable. Components follow a designed setup and build structure that allows their integration into different project hierarchies.
The Braccio environment was based largely on Specman Elite and the Verisity AHB and PCI eVCs. The eVCs were easily integrated into several ARM-based ASIC testbenches via a single configuration file for each instantiation.
Flexible method-based interface
The creation of bus-specific and transactor-independent interfaces for higher layers of a system stack proved less easily implemented. The Verisity eVCs did not offer a clean method-based interface (that is, read() and write() methods) for higher-layer protocols to use; instead, the developer was expected to use a constraint-based interface to their hidden generation and execution routines. For arbitrarily complex system stacks (such as building a device driver stack for an Ethernet controller with DMA), this proved impossible to use. Eventually, through a single-user hook and a queue, we were able to create our own flexible method-based interface.
Once a basic layered environment was in place, e was capable of providing the high-level language features to do abstract modeling of system hardware and software. A reusable configuration and status register model was created that allowed test writers to deal with registers without regard to bit-field widths and register addresses. Enumerated types made the bit-field values more abstract as well.
The e language allowed for the development of base classes and arbitrary user extendibility of those classes. Braccio created a testbench container-base class that ensured that all specific implementations had a common set of capabilities such as logging, tracing and test flows. Temporary patches to environment or design issues were often a simple import of a single patches file.
However, the lack of public and private members often compromised the integrity of the class and object hierarchies by inexperienced users and required stricter discipline than if the compiler could flag violations. Design patterns that have proven useful in large-scale C++ development such as a Singleton object were difficult to implement or could not be implemented in e.
Marc Erickson is manager, tools and methodologies at mint technology (waltham, mass.).
Copyright 2001 by CMP Media. LLC, 600 Community Drive, Manhasset, NY 11030.
Reprinted from EETIMES with permission.